The present invention relates to a delay locked loop. More particularly, the present invention relates to a delay locked loop having a high-resolution voltage controlled delay line and a phase detector with no dead zone.
In many situations, such as for sampling incoming data, it is desirable to produce a series of periodic high frequency clock signals which are based on a reference clock signal. In such situations it is often desirable to use a phase locked loop, a synchronous delay line or a delay locked loop. These devices operate to keep the periodic clock signals synchronized with the reference clock. There may be an acquisition period during which the device brings the two signals into phase, before a lock condition occurs.
An example of a delay locked loop is seen in U.S. Pat. No. 6,002,281. In this patent, a reference clock signal clkin is sent through a delay line having a series of delay elements. Each element generates a pulse so that a series of pulses at equal intervals is produced. The output of the delay line is compared to the reference clock in a phase detector to determine the phase difference between the two clock signals. The phase detector then produces either up or down signals depending on how the phase needs to be changed. These two signals control the delay elements in the delay line. By changing the delay, the phase difference is also changed, until the clock signals are locked in phase with the reference clock.
This general type of delay locked loop is well known and operates in a generally satisfactory manner to produce a series of clock signals. However there are problems associated with this type of circuit arrangement. The delay line, in particular, has a problem that the time difference between the time signals is not always uniform. For example, if it is desired to have 8 timing signals at equal intervals of 100 picoseconds, it is not uncommon for mismatches to occur in loading or due to different rise times. Thus, the intervals may actually be only 75 picoseconds or as large as 110 picoseconds To make things worse, the eighth (and final) signal latches to the initial signal of the next cycle and so assumes all of the remaining time in the 800 picosecond cycle, so that the final interval will be as large as 275 picoseconds (800xe2x88x927xc3x9775) or as small as 30 picoseconds (800xe2x88x927xc3x97110) which is unacceptable. 
Another problem occurs in the phase detector. In order to eliminate a dead zone, past systems have had both the up and down signals active at the same time. This dead zone is a phenomenon whereby the charge pump current reaches 0 at a small negative number value for the phase difference and remains at that level until a small positive number is reached. Thus, this causes a nonlinearity in the graph of the phase difference versus the charge pump current. In order to remove the dead zone, both the up and down outputs produce pulses at the same time, which lengthens the time to acquire lock.
It is thus desirable to eliminate these false pulses during acquisition conditions. During acquisition conditions both up and down signals are active with one of the signals being larger than the other. It is desirable to eliminate the smaller signal completely in order to acquire lock more quickly.